Solutions for the constraint problems.

 

Problem 1

Requirement

• 20 elements
• Range 1–100
• Unique
• Sum = 1000

class pkt;

 rand int arr[20];

 constraint c1 {
   foreach(arr[i])
     arr[i] inside {[1:100]};

   unique {arr};

   arr.sum() == 1000;
 }

endclass

---

Problem 2

Requirement

• 80% aligned
• 20% unaligned

class pkt;

 rand bit [31:0] addr;
 rand bit aligned;

 constraint c1 {
   aligned dist {1:=80, 0:=20};

   addr inside {[32'h1000:32'hFFFF]};

   if(aligned)
      addr[1:0] == 0;
   else
      addr[1:0] != 0;
 }

endclass

---

Problem 3

Requirement

• Even index = even number
• Odd index = odd number
• No adjacent equal

class pkt;

 rand int q[20];

 constraint c1 {

   foreach(q[i]) {

      if(i%2==0)
         q[i]%2==0;
      else
         q[i]%2==1;

      q[i] inside {[1:100]};
   }

   foreach(q[i])
      if(i>0)
         q[i] != q[i-1];
 }

endclass

---

Problem 4

Requirement

• Size 50-100
• First AA
• Last 55
• No AA AA pattern

class packet;

 rand bit [7:0] payload[];

 constraint c1 {

   payload.size inside {[50:100]};

   payload[0] == 8'hAA;

   payload[payload.size()-1] == 8'h55;

   foreach(payload[i])
      if(i<payload.size()-1)
         !(payload[i]==8'hAA &&
           payload[i+1]==8'hAA);
 }

endclass

---

Problem 5

Requirement

• Ascending order
• Gap > 5

class pkt;

 rand int arr[10];

 constraint c1 {

   foreach(arr[i])
      arr[i] inside {[1:100]};

   foreach(arr[i])
      if(i>0) {

         arr[i] > arr[i-1];

         arr[i]-arr[i-1] > 5;
      }
 }

endclass

---

DV Problem 6

Functional Coverage stuck at 95%

Debug flow:

1. Check uncovered bin
2. Verify bin reachable
3. Review constraints
4. Review DUT functionality
5. Create directed test
6. Check coverage sampling

Possible causes:

• Unreachable scenario
• DUT bug
• Constraint issue
• Coverage model bug

---

DV Problem 7

Scoreboard mismatch but DUT correct

Possible scoreboard bugs:

• Transaction ordering issue
• Missing transaction ID
• Race condition
• Incorrect reference model
• Queue synchronization bug
• Monitor sampling error

---

DV Problem 8

Simulation passes

Emulation fails

Silicon fails

Investigate:

• CDC
• RDC
• X propagation
• Timing violations
• Reset sequence
• Power domains
• Clock gating

Most interviewers expect CDC/RDC discussion.

---

DV Problem 9

Async FIFO fails once per 10M transactions

First suspects:

1. Pointer synchronization
2. Gray code conversion
3. CDC reconvergence
4. Full/Empty generation
5. Scoreboard bug
6. Metastability

---

DV Problem 10

100% Coverage Yet Silicon Fails

Possible reasons:

CDC issue

Coverage never modeled CDC failure.

RDC issue

Reset crossing bug.

Analog interaction

PLL issue.
Power issue.

Metastability

IR Drop

Clock glitch

Testbench assumption wrong

Missing assertion

Incorrect coverage model

Silicon-only corner

ECO bug

This is a classic senior DV interview answer.

---

Ultra Hard Matrix Problem

Requirement

10×10 Matrix

• Row sum = 100
• Column sum = 100
• Values 1-20
• No duplicates in row

Can SV solve directly?

Theoretically yes.

Practically:

rand int matrix[10][10];

would create an enormous constraint space.

Constraint solver likely struggles.

Industry Answer

Generate matrix algorithmically:

1. Randomize rows
2. Calculate column deficits
3. Adjust values
4. Post-randomize balancing

This is called a hybrid solution.