1. Why can setup timing improve while hold timing worsens after CTS?
Answer
CTS introduces clock skew. Positive skew can improve setup timing but may reduce hold margin, creating hold violations.
2. Why is hold fixing considered more difficult than setup fixing?
Answer
Hold fixes must not affect setup timing. Adding delay cells fixes hold but may create setup violations elsewhere.
3. Explain OCV, AOCV and POCV.
Answer
- OCV: Fixed derate across paths.
- AOCV: Derate depends on path depth.
- POCV: Statistical variation-based derating.
POCV is commonly used in advanced nodes.
4. What happens if clock latency is underestimated during CTS?
Answer
Post-route timing may fail because actual clock insertion delay becomes larger than predicted.
5. Why does congestion occur even when utilization is only 60%?
Answer
Poor cell distribution, macro placement, pin density, routing blockages, and high fanout nets can create local congestion.
6. What is CRPR (Clock Reconvergence Pessimism Removal)?
Answer
Removes excessive pessimism when launch and capture clocks share common clock path segments.
7. What is the difference between crosstalk delay and crosstalk noise?
Answer
- Crosstalk delay affects timing.
- Crosstalk noise creates unwanted voltage glitches.
8. Why does IR drop cause setup violations?
Answer
IR drop reduces cell operating voltage, slowing gates and increasing path delay.
9. Explain electromigration in detail.
Answer
High current density moves metal atoms over time, creating opens and shorts in interconnects.
10. Why are hold violations more common after routing?
Answer
Actual routing parasitics and clock skew become visible after route, exposing previously hidden hold problems.
11. What is useful skew and how is it applied?
Answer
Intentional clock skew is introduced to improve setup timing while maintaining hold requirements.
12. Why are multi-bit flip-flops used?
Answer
Reduce:
- Clock power
- Routing congestion
- Clock tree area
while improving power efficiency.
13. What is antenna violation?
Answer
Charge accumulation during fabrication damages transistor gate oxide before metal connections are completed.
14. How would you debug a path showing setup violation only in one corner?
Answer
Analyze:
- Cell delays
- Voltage
- Temperature
- Clock uncertainty
- OCV derates
- Crosstalk effects
to determine corner-specific failure causes.
15. You have 5000 setup violations after routing. What is your debug methodology?
Answer
A senior PD engineer typically:
- Identify worst violating paths.
- Check clock quality.
- Analyze congestion.
- Check IR drop.
- Review crosstalk.
- Optimize placement.
- Apply ECO fixes.
- Re-run STA.
- Verify all corners and modes.
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