Step 1: Analyze the Symptoms
Since:
- Coverage is high.
- Assertions are passing.
- Failure is extremely rare.
This suggests:
- CDC issue
- Race condition
- Scoreboard issue
- Pointer synchronization problem
rather than a simple RTL bug.
Step 2: Investigate FIFO Pointer Synchronization
In asynchronous FIFOs:
Write Domain -----> Synchronizer -----> Read Domain
Read Domain -----> Synchronizer -----> Write Domain
Check:
- Gray code conversion
- Synchronizer implementation
- Full flag generation
- Empty flag generation
Step 3: Check Scoreboard
Common mistake:
expected_q.pop_front();
actual_q.pop_front();
without considering timing alignment.
A scoreboard bug can produce false mismatches.
Step 4: Review CDC Analysis
Check CDC report for:
- Unsynchronized crossings
- Reconvergence paths
- Multi-bit CDC transfers
Step 5: Add Assertions
Overflow Check
property no_overflow;
@(posedge wr_clk)
!(wr_en && full);
endproperty
assert property(no_overflow);
Underflow Check
property no_underflow;
@(posedge rd_clk)
!(rd_en && empty);
endproperty
assert property(no_underflow);
Data Integrity
Every write must eventually be read.
Step 6: Investigate Rare Failure
Capture:
Random Seed
Transaction ID
Write Pointer
Read Pointer
Gray Pointer
Clock Ratio
Run:
+ntb_random_seed=<seed>
to reproduce.
Step 7: Silicon Escape Analysis
Bug may escape simulation because:
- Metastability cannot be fully modeled.
- CDC corner case is extremely rare.
- Limited simulation runtime.
- Synchronizer MTBF issue.
- Environmental variations.
0 Comments